SynaptiCAD Released High Performance Verilog 2001 Simulator

For a limited time, SynaptiCAD will be giving away free "no strings attached" 6 month licenses for VeriLogger Extreme, a high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. Free licenses will be available for both Linux and Windows versions of the simulator. Unlike the lower cost simulators typically provided with FPGA tools, SynaptiCAD's simulator is being distributed without any code that slows down the simulator when run on larger designs, making it run over 10x faster than the competition on larger simulation runs.

Not just an Evaluation License

"This is not a just an evaluation license, it's a free license that can be used for real commercial work," explains Dan Notestein, president of SynaptiCAD. "There are several established players in the simulator market, so it's not an easy market to gain a foothold. When we started this project, we knew we would need not only a better product, but also a better way to get customers to try it out and see the benefits. After giving it some thought, we decided the best way to enable designers to evaluate the simulator environment was to let them use it for free to develop real designs, since the productivity leap provided by the tool set really comes from a large number of improvements to the test and debug environment, rather than a single major enhancement that's easy to communicate in a short press release."

A Sign of the Times?

SynaptiCAD wants to make it clear that this offer is in no way a response to the current global recession, although it may be fortuitous timing, especially for new startups and engineering consultants looking to keep their initial tool investments low during this risky period. According to Donna Mitchell, VP of Marketing at SynaptiCAD, "We've actually been planning this campaign for well over two years now. We knew that we would see a large increase in our user base with this offer, so before we began the program, we wanted to be very sure we had the product not only extremely stable, but also extremely easy to use, so as to keep our support staff from being overloaded with questions and feature requests. Designing a reliable, easy-to-use simulation environment is much more difficult than it might sound, and it's only now, after working with early customers for a couple of years, that we feel that VeriLogger has reached the maturity level necessary to start this campaign."

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Gates-on-the-Fly Netlist Editor Add Schematic Back Annotation & Waveform Viewer Cross-Probing

SynaptiCAD's Gates-on-the-Fly (GOF), a Verilog netlist editor and incremental schematic viewer, has added schematic back annotation and waveform viewer cross-probing. Using one of SynaptiCAD's waveform viewers, you can view waveforms from a simulation (e.g. a VCD file) or a logic analyzer and show specific logic states annotated on GOF schematic windows. The schematic and the waveform displays are linked so that you can quickly control the simulation time that is displayed from either the schematic or the waveform windows.

Cross-Probing and Schematic Back Annotation

Once a Verilog netlist is loaded into the Gates-on-the-Fly editor, you can select and view partial sections of the netlist as a GofTrace schematic window. Then, when a waveform file has been loaded into SynaptiCAD's waveform viewer, GOF supports several methods of controlling what waveforms are shown in the waveform window from a schematic window.

Logic states at a specific simulation time can be sent and displayed on the active schematic window by right clicking in the timeline of the waveform viewer. New buttons in GOF also allow moving backwards and forwards in time to the next or previous logic change on the nets shown in the schematic or jumping directly to a user-entered time.

SynaptiCAD's Waveform Viewer

Several of SynaptiCAD's products (Timing Diagram Pro, WaveFormer Pro, BugHunter Pro, and VeriLogger Extreme) support GOF schematic annotation. If you do not own one of these products, you can download SynaptiCAD's free WaveViewer software which also supports GOF schematic annotation.

Gates-on-the-Fly Overview

Gates-on-the-Fly (GOF) graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool. Netlists sometimes require changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design. Using GOF, you can easily find and view specific logic cones in your design on a schematic to visualize just the paths you need to see without unnecessary clutter. GOF also simplifies mapping from RTL level constructs to their gate-level equivalents, so that you can pinpoint the locations where changes need to be made. GOF's ECO mode supports both graphical and script-based editing features for tracking ECO changes. Metal-only ECO operations are also supported with an automatic spare gates flow.

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